The present invention generally relates to semiconductor memory devices, and more particularly to a static semiconductor memory device in which transistors having a low threshold value are used in a column transfer gate.
In a conventional static random access memory (RAM), static memory cells are coupled to a bit line pair, and first and second transistors are coupled as bit line loads to one end of each of the bit lines on the power source voltage side. A plurality of such bit line pairs are provided, and one specific bit line pair (column) is selected by a column selection signal. The other end of each of the bit lines is coupled to respective data bus via a transistor of a column transfer gate, and a write circuit is coupled to the pair of data buses. The write circuit comprises on the ground side thereof a pair of driving transistors for entering write-in data, and on the power source voltage side thereof a pair of load transistors for coupling to the power source voltage. Word lines are coupled to the corresponding memory cells via a word line driver.
A write-in operation is carried out by selecting one specific word line by a word line selection signal and selecting a specific memory cell by the column selection signal. When one of the two write-in data becomes high, the corresponding data bus and bit line become low so that the write-in of data can be carried out with respect to the specific memory cell.
In this conventional semiconductor memory device, normal enhance transistors are used as the transistors constituting the column transfer gate. But the normal enhance transistor has a relatively high threshold value, and there is a problem in that the information on the bit line cannot be transmitted quickly to the data bus at the time of a read-out operation. In other words, at the time of the read-out operation, the bit line and the data bus have an intermediate level between the power source voltage and ground level, and a voltage level must be transmitted via the column transfer gate which is applied with a relatively low gate bias voltage. As a result, the conductance of the column transfer gate becomes insufficient, and the data transmission does not follow the information on the bit line. Because the bit line pair responds gradually, an access loss and the like occur due to the slow following characteristic.
Hence, in order to improve the speed of the data transmission from the bit line to the data bus, it is possible to conceive a device which uses light dose or non dose transistors (transistors implanted with ions for the purpose of controlling the threshold value) having a low threshold value for the transistors constituting the column transfer gate so as to quickly transmit the information on the bit line to the data bus. However, it was found that the following problems will occur when transistors having a low threshold value (or a large mutual conductance) are used for the transistors constituting the column transfer gate. Firstly, when the mutual conductance of the driving transistors in the write circuit is set to a large value so as to carry out the write-in operation to the memory cell at a high speed, the level of the bit line falls to a low level which is lower than necessary and the write recovery time becomes poor. Secondly, when the mutual conductance of the driving transistors in the write circuit are set to such a value that the level of the bit line does not fall to an unnecessarily low level in order to prevent the write recovery time from becoming poor, the speed of the write-in operation becomes slow.